Generally, increasing semiconductor yields includes identifying spatial patterns associated with defects and eliminating the source of the defects based on wafer maps that provide, for example, electrical test (e-test) or sort bin data. Current methods may either require a manual supervised process that demands a significant amount of time, or apply processes that are not suited for large sample sizes, or do not provide visual interactive results for users to explore the spatial patterns, or combinations thereof.
For simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.